1. Field of the Invention
The present invention relates to a filtering device suitable for carrying out a filter operation during motion compensation processing for compression-encoding/decoding of a moving picture, and a motion-compensating device including the filtering device.
2. Description of Related Art
Latest codecs such as H.264/AVC and VC-1 have been adopted as a standard for next-generation digital versatile disks (DVDs) and digital televisions (DTVs). In such decoding devices, a filter operation of a filter for motion-compensating prediction in a motion-compensating section may be implemented using multipliers to which Booth's algorithm is applied.
An operation time of each multiplier is equal to the sum of a time required for adding partial products to each other and a time required for absorbing a carry signal. To achieve a higher operation speed, it is necessary to reduce the processing times. To reduce the number of adders in order to reduce the processing times, it is necessary to reduce the number of partial products. A multiplier is divided into sets of a plurality of consecutive bits to generate a partial product corresponding to each set, thereby enabling a reduction in the number of partial products. A secondary Booth's algorithm is used to reduce the number of partial products. That is, a multiplier is divided into sets of two bits to form groups of three bits in total including two bits of each set and a most significant bit of a low-order set.
When the filter operation is carried out using the above-mentioned codecs, however, if the filter operation is implemented by the multipliers to which Booth's algorithm is applied, a large number of multipliers are required, leading to an increase in circuit size. Likewise, if the filter operation for generating a predicted image for inter-picture prediction in H.264 is implemented by the multipliers to which Booth's algorithm is applied, the circuit size increases.
Japanese Unexamined Patent Application Publication No. 6-44291 (Endo) discloses a discrete cosine transformer which enables a reduction in circuit size by reducing the number of multipliers as much as possible. FIG. 13 is a diagram showing the discrete cosine transformer disclosed by Endo, The discrete cosine transformer includes adders 612, 640, and 642, a difference calculation unit 610, a register 614, multiplexers 616 and 652, multiplexer-multipliers 618, 620, 622, and 634, butterfly adders 626, 628, 630, 632, 644, 646, 648, and 650, multipliers 624, 636, and 638, and a quantizer 654. Difference data is obtained as an alternating-current component of image data by the difference calculation unit 610, and the difference data thus obtained is subjected to DCT. By performing the DCT on the difference data, the number of necessary coefficients is reduced, resulting in a reduction in the number of multipliers. Furthermore, when the same coefficient is multiplied by different data, the multiplication is executed by time-sharing using the multiplexer-multipliers 618, 620, 622, and 634. Consequently, the number of multipliers can be further reduced. Moreover, when coefficients to be multiplied are multiplied in advance by values contained in a quantization table of the quantizer 654, the number of multiplications is reduced. Thus, the discrete cosine transformer as disclosed by Endo achieves high-speed operation by using characteristics of discrete cosine transform and by using the multiplication and butterfly operation.
Further, Japanese Unexamined Patent Application Publication No. 2004-258141 (Okumura) discloses a multiplication device for shortening a delay time due to a subtraction performed by a block unit arithmetic unit in a circuit that performs multiple precision arithmetic for Montgomery multiplication residue arithmetic, and that performs multiple precision arithmetic with an operation frequency maintained.
The multiplication device performs multiplication of a multiplicand A and a multiplier B that are expressed by bit patterns. The multiplication device includes: a partial product generator that generates a plurality of partial products in the secondary Booth's algorithm from the multiplicand A; an encoder that encodes the multiplier B according to the secondary Booth's algorithm and outputs a selection signal depending on a value “i” specifying three consecutive bits b2i+1, b2i, and b2i−1 of the multiplier B; a selector that selects and outputs one of the plurality of partial products in response to the selection signal; and an adder that adds partial products equal in number to “i” output from the selection circuit, and generates a multiplication result. Further, the multiplication device has an operation mode in which the encoder outputs a selection signal for selecting a partial product indicating −A when “i” is 0, and outputs a selection signal for selecting a partial product indicating 0 when “i” is a value other than 0, and the adder generates a two's complement of the multiplicand A from the partial product indicating −A, and outputs the two's complement of the multiplicand A as the multiplication result.
In the discrete cosine transformer disclosed by Endo, however, a large-scale multiplier is used to carry out multiplication at high speed, which leads to an undesirable increase in circuit size. Further, the discrete cosine transformer performs generic processing without particularly using characteristics of an image. Accordingly, to meet a demand for high operation accuracy, the circuit size of the operation unit increases, which leads to an increase in power consumption. The technique disclosed by Okumura also leads to an undesirable increase in circuit size and power consumption.